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1 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com we128k32-xxx white electronic designs 128kx32 eeprom module, smd 5962-94585 top view p in d escription i/o 0-31 data inputs/outputs a 0-16 address inputs we 1-4 write enables cs 1-4 chip selects oe output enable v cc power supply gnd ground nc not connected b lock d iagram features access times of 120*, 140, 150, 200, 250, 300ns packaging: ? 66-pin, pga type, 27.3mm (1.075") square, hermetic ceramic hip (package 400) ? 68 lead, 22.4mm sq. cqfp (g2t), 4.57mm (0.180") high, (package 509) organized as 128kx32; user configurable as 256kx16 or 512kx8 write endurance 10,000 cycles data retention ten years minimum (at +25c) commercial, industrial and military temperature ranges low power cmos automatic page write operation page write cycle time: 10ms max data polling for end of write detection hardware and software data protection ttl compatible inputs and outputs 5 volt power supply built-in decoupling caps and multiple ground pins for low noise operation weight we128k32-xg2tx - 8 grams typical WE128K32-XH1X - 13 grams typical * 120ns not available for smd product f ig . 1 p in c onfiguration for we128k32n-xh1x january 2004 rev. 9
2 white electronic designs corporation ? phoenix az ? (602) 437-1520 we128k32-xxx white electronic designs p in d escription f ig . 3 p in c onfiguration for we128k32-xg2tx b lock d iagram t op v iew the wedc 68 lead cqfp fills the same fit and function as the jedec 68 lead cqfj or 68 plcc. but it has the tce and lead inspection advantage of the cqfp form. i/o 0-31 data inputs/outputs a 0-16 address inputs we 1-4 write enables cs 1-4 chip selects oe output enable v cc power supply gnd ground nc not connected
3 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com we128k32-xxx white electronic designs a bsolute m aximum r atings t ruth t able ac t est c onditions vz is programmable from -2v to +7v. iol & ioh programmable from 0 to 16ma. tester impedance z0 = 75 ? . vz is typically the midpoint of voh and vol. iol & ioh are adjusted to simulate a typical resistive load circuit. ate tester includes jig capacitance. r ecommended o pera ting c onditions dc c haracteristics (v cc = 5.0v, v ss = 0v, t a = -55c to +125c) parameter typ unit input pulse levels v il = 0, v ih = 3.0 v input rise and fall 5 ns input and output reference level 1.5 v output timing reference level 1.5 v parameter symbol unit operating temperature t a -55 to +125 c storage temperature t stg -65 to +150 c signal voltage relative to gnd v g -0.6 to +6.25 v voltage on oe and a9 -0.6 to +13.5 v note: stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. cs oe we mode data i/o h x x standby high z l l h read data out l h l write data in x h x out disable high z/data out x x h write x l x inhibit parameter symbol min max unit supply voltage v cc 4.5 5.5 v input high voltage v ih 2.0 v cc + 0.3 v input low voltage v il -0.5 +0.8 v operating temp. (mil.) t a -55 +125 c operating temp. (ind.) t a -40 +85 c parameter symbol conditions min max unit input leakage current i li v cc = 5.5, v in = gnd to v cc 10 a output leakage current i lox32 cs = v ih , oe = v ih , v out = gnd to v cc 10 a operating supply current x 32 mode i ccx32 cs = v il , oe = v ih , f = 5mhz 250 ma standby current i sb cs = v ih , oe = v ih , f = 5mhz 2.5 ma output low voltage v ol i ol = 2.1ma, v cc = 4.5v 0.45 v output high voltage v oh i oh = -400a, v cc = 4.5v 2.4 v note: dc test conditions: vih = vcc -0.3v, vil = 0.3v c apacitance (t a = +25c) parameter symbol conditions max unit oe capacitance c oe v in = 0 v, f = 1.0 mhz 50 pf we 1-4 capacitance c we v in = 0 v, f = 1.0 mhz pf hip (pga) 20 cqfp g2t 20 cs 1-4 capacitance c cs v in = 0 v, f = 1.0 mhz 20 pf data i/o capacitance c i/o v i/o = 0 v, f = 1.0 mhz 20 pf address input capacitance c ad v in = 0 v, f = 1.0 mhz 50 pf this parameter is guaranteed by design but not tested. f ig . 4 ac t est c ircuit notes:
4 white electronic designs corporation ? phoenix az ? (602) 437-1520 we128k32-xxx white electronic designs write a write cycle is initiated when oe is high and a low pulse is on we or cs with cs or we low. the address is latched on the falling edge of cs or we whichever occurs last. the data is latched by the rising edge of cs or we, whichever occurs first. a byte write operation will automatically continue to completion. write cycle timing figures 5 and 6 show the write cycle timing relation- ships. a write cycle begins with address application, write enable and chip select. chip select is accom- plished by placing the cs line low. write enable consists of setting the we line low. the write cycle begins when the last of either cs or we goes low. the we line transition from high to low also initiates an internal 150 sec delay timer to permit page mode operation. each subsequent we transition from high to low that occurs before the completion of the 150 sec time out will restart the timer from zero. the operation of the timer is the same as a retriggerable one-shot. ac write characteristics (v cc = 5.0v, v ss = 0v, t a = -55c to +125c) write cycle parame ter symbol mi n max unit write cycle time, typ = 6ms t wc 10 ms address set-up time t as 0ns write pulse width (we or cs) t wp 100 ns chip select set-up time t cs 0ns address hold time t ah 100 ns data hold time t dh 10 ns chip select hold time t csh 0ns data set-up time t ds 50 ns output enable set-up time t oes 0ns output enable hold time t oeh 0ns write pulse width high t wph 50 ns
5 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com we128k32-xxx white electronic designs write waveforms we controlled write waveforms cs controlled fig. 6 fig. 5
6 white electronic designs corporation ? phoenix az ? (602) 437-1520 we128k32-xxx white electronic designs read the we128k32-xxx stores data at the memory location determined by the address pins. when cs and oe are low and we is high, this data is present on the outputs. when cs and oe are high, the outputs are in a high impedance state. this two line control prevents bus contention. ac read characteristics (v cc = 5.0v, v ss = 0v, t a = -55c to +125c) read waveforms oe may be delayed up to t acs - t oe after the falling edge of cs without impact on t oe or by t acc - t oe after an address change without impact on t acc . read cycle parameter symbol -120 -140 -150 -200 -250 -300 unit min max min max min max min max min max min max read cycle time t rc 120 140 150 200 250 300 ns address access time t acc 120 140 150 200 250 300 ns chip select access time t acs 120 140 150 200 250 300 ns output hold from add. change, oe or cs t oh 0 00000ns output enable to output valid t oe 0 50 0 55 0 55 0 55 0 85 0 85 ns chip select or oe to high z output t df 60 70 70 70 70 70 ns fig. 7 notes: a ddress cs oe output
7 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com we128k32-xxx white electronic designs data polling the we128k32-xxx offers a data polling feature which allows a faster method of writing to the device. figure 8 shows the timing diagram for this function. during a byte or page write cycle, an attempted read of the last byte written will result in the complement of the written data on d7 (for each chip.) once the write cycle has been completed, true data is valid on all outputs and the next cycle may begin. data polling may begin at any time during the write cycle. data polling characteristics (v cc = 5.0v, v ss = 0v, t a = -55c to +125c) data polling waveforms parameter symbol min max unit data hold time t dh 10 ns oe hold time t oeh 10 ns oe to output valid t oe 55 ns write recovery time t wr 0ns fig. 8 toggle bit: in addition to data polling another method for determining the end of a write cycle is provided. during the write operation, successive attempts to read data from the device will result in i/o 6 toggling between one and zero. once the write has completed, i/o 6 will stop toggling and valid data will be read. reading the toggle bit may begin at any time during the write cycle. note: 1. toggling either oe or cs or both oe and cs will operate toggle bit. 2. beginning and ending state of i/o6 will vary 3. any address location may be used but the address should not vary. toggle but characteristics (1) symbol parameter min max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay ns t oehp oe high pulse 150 ns t wr write recovery time 0 ns twr high z tdh toe toeh we cs oe i/o6 (2)
8 white electronic designs corporation ? phoenix az ? (602) 437-1520 we128k32-xxx white electronic designs page write operation the we128k32-xxx has a page write operation that allows one to 128 bytes of data to be written into the device and consecutively loads during the internal programming period. successive bytes may be loaded in the same manner after the first data byte has been loaded. an internal timer begins a time out operation at each write cycle. if another write cycle is completed within 150s or less, a new time out period begins. each write cycle restarts the delay period. the write cycles can be continued as long as the interval is less than the time out period. the usual procedure is to increment the least significant address lines from a0 through a6 at each write cycle. in this manner a page of up to 128 bytes can be loaded in to the eeprom in a burst mode before beginning the relatively long interval programming cycle. after the 150s time out is completed, the eeprom begins an internal write cycle. during this cycle the entire page of bytes will be written at the same time. the internal programming cycle is the same regardless of the number of bytes accessed. page write characteristics (v cc = 5.0v, v ss = 0v, t a = -55c to +125c) page mode write waveforms 1. page address must remain valid for duration of write cycle. page mode write characteristics symbol unit parameter min max write cycle time, typ = 6ms t wc 10 ms address set-up time t as 0ns address hold time (1) t ah 100 ns data set-up time t ds 50 ns data hold time t dh 10 ns write pulse width t wp 100 ns byte load cycle time t blc 150 s write pulse width high t wph 50 ns x x fig. 9
9 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com we128k32-xxx white electronic designs load data aa to address 5555 load data 55 to address 2aaa load data a0 to address 5555 load data xx to any address (4) load last byte to last address software data protection enable algorithm (1) writes enabled (2) notes: 1. data format: d7 - d0 (hex); address format: a16 - a0 (hex). 2. write protect state will be activated at end of write even if no other data is loaded. 3. write protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 128 bytes of data may be loaded. enter data protect state fig. 10
10 white electronic designs corporation ? phoenix az ? (602) 437-1520 we128k32-xxx white electronic designs hardware data protection these features protect against inadvertent writes to the we128k32-xxx. these are included to improve reliability during normal operation: a) v cc power on delay as v cc climbs past 3.8v typical the device will wait 5msec typical before allowing write cycles. b) v cc sense while below 3.8v typical write cycles are inhib- ited. c) write inhibiting holding oe low and either cs or we high inhibits write cycles. d) noise filter pulses of <8ns (typ) on we or cs will not initiate a write cycle. software data protection a software write protection feature may be enabled or disabled by the user. when shipped by white microelectronics, the we-128k32-xxx has the feature disabled. write access to the device is unrestricted. to enable software write protection, the user writes three access code bytes to three special internal locations. once write protection has been enabled, each write to the eeprom must use the same three byte write sequence to permit writing. after setting software data protection, any attempt to write to the device without the three-byte command sequence will start the internal write timers. no data will be written to the device, however, for the duration of t wc . the write protection feature can be disabled by a six byte write sequence of specific data to specific locations. power transitions will not reset the software write protection. each 128k byte block of the eeprom has indepen- dent write protection. one or more blocks may be enabled and the rest disabled in any combination. the software write protection guards against inadvertent writes during power transitions, or unauthorized modification using a prom program- mer. software data protection disable algorithm (1) exit data protect state notes: 1. data format: d7 - d0 (hex); address format: a16 - a0 (hex). 2. write protect state will be activated at end of write even if no other data is loaded. 3. write protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 128 bytes of data may be loaded. (3) load data aa to address 5555 load data 55 to address 2aaa load data 80 to address 5555 load data aa to address 5555 load data 55 to address 2aaa load data 20 to address 5555 load data xx to any address (4) load last byte to last address fig. 11
11 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com we128k32-xxx white electronic designs package 400: 66 pin, pga type, ceramic hex-in-line package, hip (h1) all linear dimensions are millimeters and parenthetically in inches
12 white electronic designs corporation ? phoenix az ? (602) 437-1520 we128k32-xxx white electronic designs package 509: 68 lead, ceramic quad flat pack, cqfp (g2t)
13 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com we128k32-xxx white electronic designs lead finish: blank = gold plated leads a = solder dip leads device grade: q = compliant m = military screened -55c to +125c i = industrial -40c to +85c c = commercial 0c to +70c package type: h1 = 1.075" sq. ceramic hex in-line package, hip (package 400*) g2t = 22.4mm ceramic quad flat pack, low profile cqfp (package 509) access time (ns) improvement mark n = no connect at pins 8, 21, 28, and 39 in hip for upgrade p = alternate pin configuration for hip package organization 128k x 32 user configurable as 256k x 16 or 512k x 8 eeprom white electronic designs corp. ordering information w e 128k32 x - xxx x x x i/o 0-31 data inputs/outputs a 0-16 address inputs we 1-4 write enables cs 1-4 chip selects oe output enable v cc power supply gnd ground nc not connected fig. 12 alternate p in c onfiguration for we128k32np-xh1x p in d escription b lock d iagram t op v iew
14 white electronic designs corporation ? phoenix az ? (602) 437-1520 we128k32-xxx white electronic designs device type speed package smd no. 128k x 32 eeprom module 300ns 66 pin hip (h1) 5962-94585 01h5x 128k x 32 eeprom module 250ns 66 pin hip (h1) 5962-94585 02h5x 128k x 32 eeprom module 200ns 66 pin hip (h1) 5962-94585 03h5x 128k x 32 eeprom module 150ns 66 pin hip (h1) 5962-94585 04h5x 128k x 32 eeprom module 140ns 66 pin hip (h1) 5962-94585 05h5x 128k x 32 eeprom module 300ns 66 pin hip (h1, p type pinout) 5962-94585 01h6x 128k x 32 eeprom module 250ns 66 pin hip (h1, p type pinout) 5962-94585 02h6x 128k x 32 eeprom module 200ns 66 pin hip (h1, p type pinout) 5962-94585 03h6x 128k x 32 eeprom module 150ns 66 pin hip (h1, p type pinout) 5962-94585 04h6x 128k x 32 eeprom module 140ns 66 pin hip (h1, p type pinout) 5962-94585 05h6x 128k x 32 eeprom module 300ns 68 lead cqfp/j (g2t) 5962-94585 01hmx 128k x 32 eeprom module 250ns 68 lead cqfp/j (g2t) 5962-94585 02hmx 128k x 32 eeprom module 200ns 68 lead cqfp/j (g2t) 5962-94585 03hmx 128k x 32 eeprom module 150ns 68 lead cqfp/j (g2t) 5962-94585 04hmx 128k x 32 eeprom module 140ns 68 lead cqfp/j (g2t) 5962-94585 05hmx

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